DocumentCode :
2511535
Title :
A new Surface Accumulation Layer Transistor (SALTran) concept for current gain enhancement in bipolar transistors
Author :
Kumar, M. Jagadesh ; Parihar, Vinod
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
fYear :
2004
fDate :
2004
Firstpage :
827
Lastpage :
831
Abstract :
In this paper we report a new Surface Accumulation Layer Transistor (SALTran) on SOI which uses the concept of surface accumulation of electrons near the emitter contact to significantly improve the current gain. Using two-dimensional device simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional lateral bipolar transistor (LBT) structure. From our simulation results it is observed that the proposed SALTran exhibits a high current gain of approximately 190 as compared to the conventional transistor which shows a current gain of only 30. We also demonstrate that the presence of the surface accumulation layer does not deteriorate the cut-off frequency as observed in the high-low emitter junction bipolar transistors. We have discussed the reasons for the improved performance of the SALTran including the complete fabrication procedure as implemented in the two-dimensional process simulator.
Keywords :
accumulation layers; bipolar transistors; semiconductor device models; Si; current gain enhancement; cutoff frequency; lateral bipolar transistor; process simulator; surface accumulation layer transistor; two dimensional device simulation; BiCMOS integrated circuits; Bipolar transistors; Contacts; Cutoff frequency; Electron emission; Fabrication; Isolation technology; Lead compounds; MOSFETs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
Type :
conf
DOI :
10.1109/ICVD.2004.1261034
Filename :
1261034
Link To Document :
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