DocumentCode
2511821
Title
The research of an efficient digital channelized receiver based on parallel architecture
Author
Liu, Xinyi ; Wang, Haifeng ; Lv, Youxin
Author_Institution
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2011
fDate
21-23 Oct. 2011
Firstpage
163
Lastpage
166
Abstract
For the non-maximum decimation of filter bank channels application, a digital channelized receiver based on parallel architecture is proposed to improve the data throughput and real-time processing ability. The simulation results verify the feasibility and effectiveness of the architecture.
Keywords
channel bank filters; electronic warfare; military communication; military computing; parallel architectures; radio receivers; real-time systems; telecommunication computing; digital channelized receiver; electronic warfare; filter bank channel application; parallel architecture; real-time processing; Bandwidth; Discrete Fourier transforms; Filter banks; Parallel architectures; Real time systems; Receivers; Throughput; channelized receiver; data throughput; non-maximum decimation; parallel architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Problem-Solving (ICCP), 2011 International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4577-0602-8
Electronic_ISBN
978-1-4577-0601-1
Type
conf
DOI
10.1109/ICCPS.2011.6092277
Filename
6092277
Link To Document