State variable model for a class of multiprocessor systems

A solution for this problem in a multiprocessor system with crossbar interconnection network, using state space approach, is examined. Identical processors, totally synchronized with system clock and communicating through common memory modules, are assumed. Simple Markov chain models the behavior of each processor. The authors have developed state and output equations for the discrete time state space model. The transition probabilities of transition matrices are computed. The test for controllability have been developed to resolve the memory contention situation of the multiprocessor systems