DocumentCode
2511886
Title
Is 3D integration the way to future dependable computing platforms?
Author
Safiruddin, Saleh ; Borodin, Demid ; Lefter, Mihai ; Voicu, George ; Cotofana, Sorin Dan
Author_Institution
Fac. of EE, Math. & CS, Delft Univ. of Technol., Delft, Netherlands
fYear
2012
fDate
24-26 May 2012
Firstpage
1233
Lastpage
1242
Abstract
Achieving dependable computing systems is becoming increasingly more difficult as CMOS integrated circuits technology scaling reaches sub-22nm ranges and faces physical limitations. Dependable computing is also a major concern with the various new technologies that are being investigated to overcome the physical limitations of CMOS technology. 3D integration, though initially proposed as a way of achieving speedup of integrated circuits without the need for scaling, offers many new opportunities for dependable computing. 3D integration adds two new dimensions to the design space: (i) the z-dimension, as now the application can be mapped on parts of the circuit that are placed in different planes, and (ii) the R-dimension as different planes can be selected with different reliabilities. This greatly expands the solution space and provides many opportunities to deal with new and existing challenges. In this paper we identify important strategies to achieve dependable computing by exploring the opportunities that 3D integration offers. We present systems level approaches for alleviating underlying technology reliability shortcomings and investigate the opportunities opened up by TSV-based 3D integration with emphasis on the system reliability point of view. Our investigation clearly indicates that the proposed 3D dependable computing paradigms, if developed and further explored, can facilitate the continuation of the trend of reducing package size and increasing transistor densities, and allow for the successful utilization of novel emerging unreliable devices.
Keywords
reliability; three-dimensional integrated circuits; transistors; 3D dependable computing paradigm; TSV-based 3D integration; computing platform; package size; system reliability; technology reliability shortcoming; transistor density; Circuit faults; Hardware; Integrated circuit reliability; Redundancy; Transistors; Wires; 3D integration; dependable computing; fault tolerance; reliability; through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Optimization of Electrical and Electronic Equipment (OPTIM), 2012 13th International Conference on
Conference_Location
Brasov
ISSN
1842-0133
Print_ISBN
978-1-4673-1650-7
Electronic_ISBN
1842-0133
Type
conf
DOI
10.1109/OPTIM.2012.6231859
Filename
6231859
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