Computing silent gate models for noise analysis from slew and delay tables

In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models with which the gate can be replaced when its output is steady HIGH or steady LOW. Traditional ASIC libraries are characterized for slew and delay for static timing signoff. These represent the behavior of gates during switching. However, for noise analysis we require models for gates when the output is stable. The objective of this work is to derive such models from circuits characterized for slew. This enables a designer to stay in the familiar STA (Static Timing Analysis) environment and perform noise analysis. We write the non-linear current-voltage relationship of the conducting PMOS or NMOS transistor. This relationship is interpreted as a non-linear resistor. We use it to compute output transition times in a simplified circuit. These transition times are matched with appropriate entry in slew table for the gate. The value of nonlinear resistor is calculated from this match. The limiting value of this non-linear resistor gives the steady state resistance. The resistance values are compared with those obtained using HSPICE simulation. An excellent match is observed. These resistances are used during noise analysis. For better accuracy a voltage dependent form of these resistors can be used, which results in a non-linear circuit to be analyzed. An efficient method is detailed which uses reduced order models for the interconnect, non-linear port resistance models for the silent gates and standard Thevenin source models for the transitioning aggressor gates. Equations are formulated in a manner that leads to a positive definite matrix. It facilitates iterative methods like Gauss Seidel for fast solution. Experimental results with 0.13 μm industry examples are given to support the suggested methods.