• DocumentCode
    2512265
  • Title

    Armstrong II: a loosely coupled multiprocessor with a reconfigurable communications architecture

  • Author

    Athanas, Peter M. ; Silverman, Harvey F.

  • Author_Institution
    Div. of Eng., Brown Univ., Providence, RI, USA
  • fYear
    1991
  • fDate
    30 Apr-2 May 1991
  • Firstpage
    385
  • Lastpage
    388
  • Abstract
    The Armstrong II processing node is a new addition to the Armstrong multiprocessor system. This new design greatly enhances the processing and network performance, yet is relatively simple, inexpensive and easily reproduced. Network performance is improved through the addition of a dedicated communications processor closely linked with a reconfigurable element, which allows testing of different communication architectures after the board is fabricated, and also provides a bridge not only to previously designed processing nodes, but also to future nodes
  • Keywords
    multiprocessing systems; performance evaluation; Armstrong II; dedicated communications processor; loosely coupled multiprocessor; network performance; processing nodes; reconfigurable communications architecture; Bandwidth; Bridge circuits; Communication effectiveness; Design engineering; Field programmable gate arrays; Laboratories; Multiprocessing systems; Process design; System testing; Systems engineering and theory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1991. Proceedings., Fifth International
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    0-8186-9167-0
  • Type

    conf

  • DOI
    10.1109/IPPS.1991.153808
  • Filename
    153808