Effect of voltage scaling on soft error protection methods for SRAMs

As voltage and process technology scales the critical charge, Qcrit, rapidly decreases for SRAM cells. The SEU protection methods that are currently used to increase the level of protection of the SRAM cells do not factor in performance and power consumption optimization. In this paper, we analyze the tradeoffs of voltage scaling between performance, power and SEU reliability for standard hardened cell, an alternative power efficient SRAMT cell for 32nm and 45nm, and a capacitive-based cell for 130nm process technologies. We also introduce a design space exploration and comparison technique with the goal to produce an optimized SRAM design using various SEU protection methods based on a set of specifications (performance, power consumption, SEU reliability, process technology, supply voltage) for a specific design.