Low power dissipation logic inverter design using atomic-level width controlled GNR-FETs

In this paper we propose a digital logic inverter based on Graphene Nanoribbon Field Effect Transistor (GNR-FET) using ratioed circuit topology. Different types of GNR-FET architectures have been analysed through their current-voltage characteristics to find their probable applications like interconnect, on-chip resistance etc. Here electronic transport calculation is based on NEGF approach which is coupled with Poisson´s equation to incorporate the effects of self-consistent field. Our all-graphene inverter shows output voltage swing of ~0.8V for an input voltage swing of 1V having a noise margin of 0.2V with a rise time of ~14.4ps and fall time of ~1.78ps. When it operates in 10GHz and 80% duty cycle the total power consumption is ~100nW which seems promising for low power logic design.