Analytical modeling of accumulation layer thickness in SOI G4FET: Introducing geometric factor

An analytical model has been developed to determine the accumulation layer thickness of an inverted back interface silicon-on-insulator (SOI) four-gate transistor (G⁴ - FET) by solving two dimensional Poisson´s equation. To do so a geometric factor is introduced that combines the neglected inversion effects along with the existing device physics. Moreover, this factor considers the charge redistribution due to change in bias condition in different electrodes of the device. Physically, it indicates the non-availability of space for both depleted and inverted charges. The proposed model, named as modulated model for accumulation thickness considering inversion effects is verified numerically. The model commenced here successfully correlates the effect of all four gate bias.