DocumentCode
2514424
Title
A generic floorplanning methodology
Author
Mortazavi, Mobammad ; Bourbakis, Nikolaos G.
Author_Institution
Dept. EE, Binghampton Univ., NY, USA
fYear
1994
fDate
20-22 Sep 1994
Firstpage
749
Lastpage
763
Abstract
One of the important and time consuming stages of design automation is the physical layout design cycle. The physical layout cycle itself consists of several steps, such as partitioning, floorplanning, placement, synthesis, muting and compaction. In this paper, a generic floorplanning methodology is presented. The methodology is based on the hierarchical cooperation of two context-free languages (SCAN and GEOMETRIA). In order to achieve an acceptable planning, the SCAN language defines the partitioning of the floor area and the global acquisition strategy (scan patterns) for the placement of the macro blocks. On the other hand, GEOMETRIA language deals with the local synthesis of the block under the constraints superimposed by global scan patterns. The results obtained by this methodology are very promising in comparison with other floorplanning methodologies
Keywords
VLSI; circuit layout CAD; context-free languages; design for testability; integrated circuit layout; GEOMETRIA language; SCAN language; compaction; context-free languages; design automation; floorplanning; generic floorplanning methodology; global acquisition strategy; grammar; hierarchical cooperation; macro blocks; muting; partitioning; physical layout design; placement; scan patterns; synthesis; time consuming stages; Chip scale packaging; Circuit synthesis; Compaction; Controllability; Design automation; Design for testability; Design methodology; Strategic planning; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
AUTOTESTCON '94. IEEE Systems Readiness Technology Conference. 'Cost Effective Support Into the Next Century', Conference Proceedings.
Conference_Location
Anaheim, CA
Print_ISBN
0-7803-1910-9
Type
conf
DOI
10.1109/AUTEST.1994.381541
Filename
381541
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