Title :
An efficient signature loading mechanism for memory repair
Author_Institution :
Synopsys, Yerevan, Armenia
Abstract :
Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.
Keywords :
built-in self test; integrated circuit reliability; integrated circuit testing; storage management chips; BISR; BIST; built-in self-repair; built-in self-test; embedded memories test; hard repair flow; memory repair organization time reduction; memory repair signature delivery process; memory repair signature loading mechanism; Built-in self-test; Containers; IP networks; Loading; Maintenance engineering; Registers; System-on-chip;
Conference_Titel :
Design & Test Symposium (EWDTS), 2014 East-West
Conference_Location :
Kiev
DOI :
10.1109/EWDTS.2014.7027061
