DocumentCode
251550
Title
An efficient signature loading mechanism for memory repair
Author
Sargsyan, Vrezh
Author_Institution
Synopsys, Yerevan, Armenia
fYear
2014
fDate
26-29 Sept. 2014
Firstpage
1
Lastpage
4
Abstract
Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.
Keywords
built-in self test; integrated circuit reliability; integrated circuit testing; storage management chips; BISR; BIST; built-in self-repair; built-in self-test; embedded memories test; hard repair flow; memory repair organization time reduction; memory repair signature delivery process; memory repair signature loading mechanism; Built-in self-test; Containers; IP networks; Loading; Maintenance engineering; Registers; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2014 East-West
Conference_Location
Kiev
Type
conf
DOI
10.1109/EWDTS.2014.7027061
Filename
7027061
Link To Document