• DocumentCode
    251561
  • Title

    Combinational part structure simplification of fully delay testable sequential circuit

  • Author

    Matrosova, A. ; Mitrofanov, E. ; Roumjantseva, E.

  • Author_Institution
    Dept. of Appl. Math. & Cybern., Tomsk State Univ., Tomsk, Russia
  • fYear
    2014
  • fDate
    26-29 Sept. 2014
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are considered. They are based on using corrected Free BDDs instead of ROBDDs and factorizing monotonous products. Some experimental results are given.
  • Keywords
    logic design; logic testing; sequential circuits; ROBDD; corrected free BDD; delay testability; delay testable sequential circuit; sequential circuit design; Boolean functions; Circuit faults; Data structures; Delays; Logic gates; Robustness; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Test Symposium (EWDTS), 2014 East-West
  • Conference_Location
    Kiev
  • Type

    conf

  • DOI
    10.1109/EWDTS.2014.7027068
  • Filename
    7027068