DocumentCode :
2515797
Title :
Veiling Luminance estimation on FPGA-based embedded smart camera
Author :
Grana, Constantino ; Borghesani, Daniele ; Santinelli, Paolo ; Cucchiara, Rita
Author_Institution :
DII, Univ. degli Studi di Modena e Reggio Emilia, Modena, Italy
fYear :
2012
fDate :
3-7 June 2012
Firstpage :
334
Lastpage :
339
Abstract :
This paper describes the design and development of a Veiling Luminance estimation system based on the use of a CMOS image sensor, fully implemented on FPGA. The system is composed of the CMOS Image sensor, FPGA, DDR SDRAM, USB controller and SPI (Serial Peripheral Interface) Flash. The FPGA is used to build a system-on-chip integrating a soft processor (Xilinx MicroBlaze) and all the hardware blocks needed to handle the external peripherals and memory. The soft processor is used to handle image acquisition and all computational tasks need to compute the Veiling Luminance value. The advantages of this single chip FPGA implementation include the reduction of the hardware requirements, power consumption, and system complexity. The problem of the high dynamic range images have been addressed with multiple acquisitions at different exposure times. Vignetting, radial distortion and angular weighting, as required by veiling luminance definition, are handled by a single integer look-up table (LUT) access. Results are compared with a state of the art certified instrument.
Keywords :
CMOS image sensors; DRAM chips; cameras; digital signal processing chips; field programmable gate arrays; image processing; peripheral interfaces; road safety; system-on-chip; traffic engineering computing; tunnels; CMOS image sensor; DDR SDRAM; FPGA; SPI; USB controller; Xilinx MicroBlaze; angular weighting; computational task; driving safety; embedded smart camera; external peripheral handling; hardware requirement reduction; high dynamic range image; image acquisition; power consumption reduction; radial distortion; serial peripheral interface flash; single integer look-up table access; soft processor; system complexity reduction; system-on-chip; tunnel; veiling luminance estimation system; vignetting; Cameras; Estimation; Field programmable gate arrays; Gray-scale; Lighting; Nonlinear distortion; Optical distortion;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Vehicles Symposium (IV), 2012 IEEE
Conference_Location :
Alcala de Henares
ISSN :
1931-0587
Print_ISBN :
978-1-4673-2119-8
Type :
conf
DOI :
10.1109/IVS.2012.6232154
Filename :
6232154
Link To Document :
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