Title :
Functional failure analysis of logic LSIs from backside of the chip and its verification by logic simulation
Author :
Ishii, T. ; Inoue, M. ; Asatani, N. ; Naitoh, K. ; Mitsuhashi, J.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A novel technique has been developed for fault isolation in logic LSIs. The technique is constructed using backside infra-red light detection through the silicon chip by an emission microscope, which is connected to an automated test equipment (ATE), and linked to a CAD layout pattern view system which assists the chip backside image and logic simulation for fault verification. This technique can perform an exact functional failure analysis from the backside of the chip
Keywords :
automatic test equipment; automatic testing; circuit analysis computing; digital integrated circuits; failure analysis; fault location; infrared imaging; integrated circuit testing; integrated logic circuits; large scale integration; logic testing; microscopy; ATE; CAD layout pattern view system; Si chip; automated test equipment; backside infrared light detection; chip backside image; dEMS method; emission microscope; fault isolation; fault verification; functional failure analysis; logic LSIs; logic simulation; Circuit faults; Circuit testing; Electrical fault detection; Failure analysis; Image analysis; Large scale integration; Logic testing; Medical services; Microscopy; Silicon;
Conference_Titel :
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on
Print_ISBN :
0-7803-3985-1
DOI :
10.1109/IPFA.1997.638068
