DocumentCode :
2515939
Title :
Buffer depth and traffic influence on 3D NoCs performance
Author :
Ghidini, Yan ; Webber, Thais ; Moreno, Edson ; Grando, Fernando ; Fagundes, Rubem ; Marcon, César
Author_Institution :
Fac. of Inf., Pontifical Catholic Univ. of Rio Grande do Sul (PUCRS), Porto Alegre, Brazil
fYear :
2012
fDate :
11-12 Oct. 2012
Firstpage :
9
Lastpage :
15
Abstract :
3D NoC-based architectures have emerged to reduce the network latency, the energy consumption and total area in comparison to 2D NoC topologies. However, they are characterized by various trade-offs with regard to the three dimensional structure and its performance specifications. In this paper, we present a 3D NoC mesh architecture called Lasio, whose latency and the throughput achieved, for both network and application, are evaluated considering two types of traffic patterns, varied buffer depth and a range of packet sizes. Cycle-accurate simulations demonstrated that there is a high impact of buffer depth and packet size on the NoC latency and on the application latency. Applying an appropriate buffer depth, for several sizes of packets, the application latency is reduced and throughput is increased.
Keywords :
network-on-chip; three-dimensional integrated circuits; 2D NoC topologies; 3D NoC mesh architecture; Lasio; buffer depth; energy consumption; network latency; traffic influence; Clocks; Energy consumption; Routing; Switches; Throughput; Topology; 3D NoC; buffer depth; latency; throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Rapid System Prototyping (RSP), 2012 23rd IEEE International Symposium on
Conference_Location :
Tampere
ISSN :
2150-5500
Print_ISBN :
978-1-4673-2786-2
Electronic_ISBN :
2150-5500
Type :
conf
DOI :
10.1109/RSP.2012.6380684
Filename :
6380684
Link To Document :
بازگشت