Title :
Analog VLSI design of cellular neural networks with annealing agility
Author :
Sheu, Bing J. ; Bang, Sa H. ; Fang, Wai-Chi
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications
Keywords :
CMOS analogue integrated circuits; VLSI; annealing; cellular neural nets; CMOS VLSI design; analog VLSI design; annealing agility; cellular neural networks; continuous-time shift-invariant CNN; digitally-programmable operators; local interconnection; synaptic operators; Annealing; Cellular neural networks; Hardware; Integrated circuit interconnections; Laboratories; Neural engineering; Neurons; Propulsion; Very large scale integration; Voltage;
Conference_Titel :
Cellular Neural Networks and their Applications, 1994. CNNA-94., Proceedings of the Third IEEE International Workshop on
Conference_Location :
Rome
Print_ISBN :
0-7803-2070-0
DOI :
10.1109/CNNA.1994.381644
