Temperature aware test scheduling by modified floorplanning

The semiconductor industry is always looking for some new technology in order to house the ever increasing number of devices in as small area as possible. One such solution is offered by the three dimensional SoCs which is vertical stacking of the various dies. It also has associated with it various challenges and constraints which need to be overcome before its adoption. Power density is also increasing, resuling in increased heat as more and more functions are being realised in a single chip. Cooling methods have to be adopted. Again testing results in more heat generation than functional mode of the chip. In this paper we have tried to analyze the effect of floorplanning on the maximum temperature. The benchmark circuit d695 has been taken and difference of temperature between various floorplans has been obtained. It shows here that the difference in temperature can be as high as 38K for a modified floorplan compared to original one.