Extending fault periodicity table for testing faults in memories under 20nm

Author

Harutyunyan, G. ; Shoukourian, S. ; Vardanian, V. ; Zorian, Y.

Author_Institution

Synopsys, Yerevan, Armenia

fYear

2014

fDate

26-29 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

A new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms was introduced recently. These rules are represented in a form of a Fault Periodicity Table (FPT) considering both known and unknown memory faults in one table. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. In this paper, application of the proposed methodology for description of memory faults in technologies below 20nm, including 16/14nm FinFET-based memories, is shown. Specifically, it is shown that all recently discovered FinFET-specific faults successfully fit into FPT.

Keywords

MOSFET circuits; built-in self test; integrated circuit reliability; integrated circuit testing; storage management chips; FPT; FinFET-based memories; fault periodicity table; fault sensitization complexity; fault testing; memory BIST infrastructure; memory faults; size 14 nm; size 16 nm; size 20 nm; test algorithms; Buildings; Built-in self-test; Complexity theory; FinFETs; Logic gates; Random access memory; FinFET; March test; built-in self-test; fault periodicity;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Test Symposium (EWDTS), 2014 East-West

Conference_Location

Kiev

Type

conf

DOI

10.1109/EWDTS.2014.7027088

Filename

7027088