29 ps ECL circuits using U-groove isolated SICOS technology

Author

Shiba, T. ; Tamaki, Y. ; Ogiwara, I. ; Kure, T. ; Kobayashi, T. ; Yagi, K. ; Tanabe, M. ; Nakamura, T.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

225

Lastpage

228

Abstract

A 0.5- mu m SICOS (sidewall base contact structure) technology is discussed. U-groove isolation technology and 0.5- mu m fabrication technology reduce the transistor size to 60 mu m/sup 2/. The use of a reduced-resistance base polysilicon electrode and a shallow epitaxial layer improves the emitter-coupled logic (ECL) gate delay time by 20% and 30%, respectively. A typical gate delay time of 29 ps and a minimum gate delay time of 27 ps at a switching current of 1.2 mA and an emitter size of 0.4 mu m*2.4 mu m were realized. This U-groove isolated SICOS device is suitable for very-high-speed VLSIs.<>

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; semiconductor technology; 0.4 micron; 0.5 micron; 1.2 mA; 29 to 27 ps; ECL circuits; U-groove isolated SICOS technology; U-groove isolation technology; emitter size; emitter-coupled logic; gate delay time; gate propagation delay; reduced-resistance base polysilicon electrode; shallow epitaxial layer; sidewall base contact structure; switching current; transistor size; very-high-speed VLSIs; Amorphous silicon; Circuits; Cutoff frequency; Delay effects; Electrodes; Epitaxial layers; Etching; Fabrication; Isolation technology; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74266

Filename

74266