DocumentCode
2516242
Title
10 nm-gate-length transistors on ultra-thin SOI film: process realization and design optimisation
Author
Lolivier, J. ; Vinet, M. ; Poiroux, T. ; Previtali, B. ; Chevolleau, T. ; Hartmann, J.M. ; Papon, A.M. ; Truche, R. ; Faynot, O. ; Balestra, F. ; Deleonibus, S.
Author_Institution
DRT, CEA, Grenoble, France
fYear
2004
fDate
4-7 Oct. 2004
Firstpage
17
Lastpage
18
Abstract
We demonstrate ultra-thin SOI nMOSFETs with silicon thinned down to 8 nm and gate length as short as 10 nm. TTSD (to control access resistance) and pocket implantation (to extend scaling limits) are validated down to 10 nm. This performance, reported on different devices, evidences the possibility of UTSOI devices.
Keywords
MOSFET; elemental semiconductors; semiconductor device models; silicon-on-insulator; thin films; 10 nm; 10 nm gate length transistors; 8 nm; Si; control access resistance; design optimisation; pocket implantation; scaling limits; ultrathin SOI MOSFET; ultrathin SOI film; Conductivity; Contact resistance; Design optimization; Fluctuations; MOSFETs; Process design; Silicon; Surface resistance; Thickness control; Thickness measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN
0-7803-8497-0
Type
conf
DOI
10.1109/SOI.2004.1391536
Filename
1391536
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