A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

We present a new synthesis and partitioning approach for multiple-FPGA implementations from register-transfer-level (RTL) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and partitioning method which fully exploits the design structural hierarchy by decomposing RTL components into sets of logic sub-functions. This allows the partitioner to place portions of components into FPGA partitions. Experimental results on a number of benchmarks and industrial designs show that our approach achieves significant improvements in CLB and IO-pin utilizations of FPGAs compared to that produced using a traditional multiple-FPGA partitioning method.