Fabrication of strained Si/strained SiGe/strained Si heterostructures on insulator by a bond and etch-back technique

Author

Åberg, I. ; Olubuyide, O.O. ; Li, J. ; Hull, R. ; Hoyt, J.L.

Author_Institution

MIT Microsyst. Technol. Lab., Cambridge, MA, USA

fYear

2004

fDate

4-7 Oct. 2004

Firstpage

35

Lastpage

36

Abstract

This paper discusses the fabrication of strained Si/strained SiGe/strained Si heterostructures on insulator by a bond and etch-back technique with total thickness of 25 nm. We have shown that the etch back process does not roughen the surface. By secondary ion mass spectroscopy (SIMS), we have shown a reduction in peak Ge fraction from the as grown 55% to 50% as a result of thermal processing.

Keywords

Ge-Si alloys; MOSFET; chemical vapour deposition; elemental semiconductors; etching; secondary ion mass spectra; semiconductor growth; semiconductor heterojunctions; semiconductor thin films; silicon; silicon-on-insulator; 25 nm; SIMS; Si-SiGe-Si; SiGe etching; etch-back process; secondary ion mass spectroscopy; silicon on insulator; strained Si-SiGe-Si heterostructure fabrication; thermal processing; Bonding; Charge carrier processes; Electron mobility; Etching; Fabrication; Germanium silicon alloys; Insulation; MOSFETs; Materials science and technology; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2004. Proceedings. 2004 IEEE International

Print_ISBN

0-7803-8497-0

Type

conf

DOI

10.1109/SOI.2004.1391544

Filename

1391544