Dynamic-Vt, dual-power-supply SRAM cell using D2G-SOI for low-power SoC application

Author

Yamaoka, Masanao ; Osada, Kenichi ; Itoh, Kiyoo ; Tsuchiya, Ryuta ; Kawahara, Takayuki

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

2004

fDate

4-7 Oct. 2004

Firstpage

109

Lastpage

111

Abstract

In this paper, new SRAM cells are proposed to lower the operable Vdd with improving the soft-error rate (SER), static-noise margin (SNM), writing margin, and cell current. The cells feature uses of a new fully-depleted (FD) SOI, called dynamic-double-gate SOI (D2G-SOI), and uses dual power supply to boost the word-line voltage and power supply while bit-line voltage is maintained low to keep power consumption low.

Keywords

CMOS memory circuits; SRAM chips; elemental semiconductors; integrated circuit noise; silicon-on-insulator; system-on-chip; D2G-SOI; Si; bit line voltage; cell current; dual power supply SRAM cell; dynamic double gate-SOI; fully depleted SOI; low-power SoC application; power consumption; silicon-on-insulator; soft-error rate; static-noise margin; word line voltage; writing margin; Circuits; Energy consumption; Intrusion detection; Laboratories; MOSFETs; P-n junctions; Power supplies; Random access memory; Stability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2004. Proceedings. 2004 IEEE International

Print_ISBN

0-7803-8497-0

Type

conf

DOI

10.1109/SOI.2004.1391578

Filename

1391578

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2517099