Title :
Novel high-density low-power high-performance double-gate logic techniques
Author :
Chiang, Meng-Hsueh ; Kim, Keunwoo ; Tretz, Christophe ; Chuang, Ching-Te
Author_Institution :
Nat. Ilan Univ., Taiwan
Abstract :
This paper propose novel double-gate (DG) logic circuit schemes using only symmetrical gates to reduce the area and leakage/active power. The performance improvement and power reduction for NAND, NOR, and pass-gate are studied via the two-dimensional numerical device simulator to directly simulate the circuit structures.
Keywords :
NAND circuits; NOR circuits; logic gates; logic simulation; low-power electronics; NAND gate; NOR gate; active power reduction; circuit structure simulation; double-gate logic circuit; leakage power; pass gate; symmetrical gates; two-dimensional numerical device simulator; Back; Capacitance; Delay; Design engineering; Energy consumption; FinFETs; Logic circuits; Logic devices; Logic functions; Threshold voltage;
Conference_Titel :
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN :
0-7803-8497-0
DOI :
10.1109/SOI.2004.1391583
