DocumentCode :
2517264
Title :
A Numerical Study on Heat Flow and Load Distribution During Chip to Wafer or Wafer to Wafer Bonding in Vacuum
Author :
Malecki, Krzysztof ; Pikur, Lukasz ; Falat, Tomasz ; Bock, Gemot ; Hillmann, Gerhard ; Sigl, Alfred ; Marenco, Norman ; Friedel, Kazimierz
Author_Institution :
Wroclaw Univ. of Technol., Wroclaw, Poland
fYear :
2008
fDate :
9-12 Dec. 2008
Firstpage :
18
Lastpage :
23
Abstract :
In this paper Authors report the implementation of a Finite Element Method (FEM) in modelling the heat flow and the deformation of the main part of the bonding machine, the work undertaken in order to develop and optimize the technology for innovative waferlevel vacuum packaging process, addressed to high volume System-in-Package (SiP) production. The investigated new approach is based on two step MEMS (Micro Electro-Mechanical Systems) to ASIC (Application Specific Integrated Circuit) integration, realised by means of prototyped bonding station, the EVG540, developed by EVG Group [1]. The design of experiment was carried out by Taguchi method. The relation between heat flow in analyzed system and bonding setups configuration (different compliant conditions), unit design (heat sinks, thermal insulation), materials properties (heat conductivity, emissivity, and coefficient of thermal expansion - CTE) and process conditions (vacuum level, heaters power supply, force load, and process duration) was identified and studied. The obtained results showed correlation to the bonding experimental process and confirmed the usability of the developed model. As a result, the process conditions (temperature, force load, setup configuration) were determined, and the overall bonding process can be optimized.
Keywords :
Taguchi methods; application specific integrated circuits; design of experiments; emissivity; finite element analysis; heat conduction; heat sinks; micromechanical devices; system-in-package; thermal expansion; thermal insulation; wafer bonding; wafer-scale integration; ASIC; MEMS; Taguchi method; application specific integrated circuit; chip-to-wafer bonding; design of experiment; emissivity; finite element analysis; force load; heat conductivity; heat flow; heat sinks; load distribution; microelectro-mechanical systems; power supply; process duration; system-in-package; thermal expansion coefficient; thermal insulation; vacuum level; wafer-to-wafer bonding; Application specific integrated circuits; Finite element methods; Heat sinks; Optimized production technology; Thermal conductivity; Thermal expansion; Thermal force; Thermal loading; Vacuum systems; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2117-6
Electronic_ISBN :
978-1-4244-2118-3
Type :
conf
DOI :
10.1109/EPTC.2008.4763406
Filename :
4763406
Link To Document :
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