DocumentCode
2517299
Title
Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies
Author
Beyne, Eric
Author_Institution
IMEC, Leuven, Belgium
fYear
2008
fDate
9-12 Dec. 2008
Firstpage
29
Lastpage
34
Abstract
3D integration technologies using through-Si via (TSV) technologies are receiving increased interest. A wide diversity of technologies is being proposed and an increasing number of potential application areas are identified. Different application domains have different TSV requirements and justify different integration approaches. The most important challenges to a widespread use of 3D integration technologies are related to the economics of the 3D TSV and stacking processes, the availability of suitable equipment for large scale production and the possible negative impact on the device quality and reliability of the TSV processing.
Keywords
elemental semiconductors; integrated circuit reliability; semiconductor device reliability; silicon; Si; device quality; economical barriers; large scale production; reliability; stacking processes; technical barriers; through-Si-via 3D integration technologies; Assembly; Availability; Electronics packaging; Integrated circuit interconnections; Large-scale systems; Stacking; Through-silicon vias; Wafer bonding; Wafer scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location
Singapore
Print_ISBN
978-1-4244-2117-6
Electronic_ISBN
978-1-4244-2118-3
Type
conf
DOI
10.1109/EPTC.2008.4763408
Filename
4763408
Link To Document