Strained-Si/SiGe-on-insulator wafers fabricated by Ge-condensation process

Author

Hirashita, N. ; Numata, T. ; Tezuka, T. ; Sugiyama, N. ; Usuda, K. ; Irisawa, T. ; Tanabe, A. ; Moriyama, Y. ; Nakaharai, S. ; Takagi, S. ; Toyoda, E. ; Miyamura, Y.

Author_Institution

MIRAI-ASET, Kawasaki, Japan

fYear

2004

fDate

4-7 Oct. 2004

Firstpage

141

Lastpage

142

Abstract

This work presents successful fabrication of uniform 150 and 200 mm strained-Si/SiGe-on-insulator wafers by using the Ge-condensation process and discusses some integration issues. Epitaxial growth of both SiGe and Si films was performed at 600 °C in 1 Pa by a mixture of SiH₄, GeH₄, and H₂ using LPCVD system with vertical reactor type. CMOS devices were also fabricated to examine the material quality of the 150 and 200 mm SSOI wafers and commercially available SOI. Poly-Si gate CMOS process with 10 nm thick gate oxide was employed in this work.

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; chemical vapour deposition; condensation; elemental semiconductors; semiconductor epitaxial layers; semiconductor growth; silicon-on-insulator; wafer-scale integration; 1 Pa; 10 nm; 150 mm; 200 mm; 600 degC; CMOS device; Ge condensation process; LPCVD system; SOI wafer; Si-SiGe; SiGe films; epitaxial growth; low pressure chemical vapor deposition; poly-Si gate CMOS process; strained-Si/SiGe-on-insulator wafer fabrication; thick gate oxide; vertical reactor; Atomic layer deposition; CMOS process; Ceramics; FETs; Fabrication; Germanium silicon alloys; MOSFETs; Semiconductor films; Silicon germanium; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2004. Proceedings. 2004 IEEE International

Print_ISBN

0-7803-8497-0

Type

conf

DOI

10.1109/SOI.2004.1391591

Filename

1391591