Width minimization of two-dimensional CMOS cells using integer programming

We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Runtimes for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.