Technique for rapid, in-line characterization of switching history in partially depleted SOI technologies

Switching history arising from body potential deviations in partially depleted (PD) SOI devices is a key technology performance metric and real-time feedback on switching history trends is important in reducing SOI technology development cycle times. Detailed switching history can be obtained from time resolved gate delay measurements but these are ill-suited to in-line test in terms of lack of automation, required equipment or test time. We have developed a technique and circuit to enable the in-line measurement of average switching history to an accuracy of a few percent - sufficient for process development needs. The circuit requires only "DC" inputs, is self-timed, self-calibrating and tested with conventional in-line parametric testers.