DocumentCode
2517693
Title
DRAM bit-line coupling noise analysis and simulation of process sensitivity for COB scheme
Author
Li-Fu Chang ; Min-Hwa Chi
Author_Institution
Vanguard Int. Semicond. Corp., Hsinchu, Taiwan
fYear
1998
fDate
19-21 Oct. 1998
Firstpage
186
Lastpage
189
Abstract
The bit-line coupling capacitance and the process sensitivity of the 8F/sup 2/ cell in the COB scheme are critical issues for future advanced DRAM. In this paper, these issues and design curves of bit-line coupling capacitance of an 8F/sup 2/ cell in the COB scheme are investigated by 3D simulation and an analytical model.
Keywords
DRAM chips; capacitance; integrated circuit modelling; integrated circuit noise; 3D simulation; COB scheme; DRAM bit-line coupling noise; analytical model; coupling capacitance; process sensitivity; Analytical models; Capacitance; Capacitors; Conductors; Dielectric substrates; Electrodes; Plugs; Process design; Random access memory; Semiconductor device noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on
Conference_Location
Osaka, Japan
Print_ISBN
0-7803-4369-7
Type
conf
DOI
10.1109/IWCE.1998.742743
Filename
742743
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