Novel process for fully self-aligned planar ultrathin body Double-Gate FET

We present a process for the ideal planar ultrathin body DGFET structure with the top and bottom gates fully self-aligned to each other and with low parasitic capacitance to the flared-out source/drain. The process begins with epitaxial growth of a SiGe/Si/SiGe trilayer on a thin N+ doped SOI substrate followed by deposition of an insulating cap layer. Key process steps have been developed and functional transistors are obtained.