Design, Assembly and Reliability of Large Die (21 x 21mm2) and Fine-pitch (150pm) Cu/Low-K Flip Chip Package

This paper focused on design, assembly and reliability assessments of 21 × 21 mm² Cu/Low-K Flip Chip (65 nm technology) with 150 ¿m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97.5Sn2.5Ag), High-Pb (95Pb5Sn) and Cu-post/95Pb5Sn. Two different die thicknesses, such as 750 ¿m and 300 ¿m, were evaluated. the flip chip assembly of high-pb test vehicles required the right choice of flux and special alignment between the high-pb solder bumps and substrate presolder to ensure proper solder bumps and substrate pre-solder alloy wetting. Finite Element Modeling (FEM) was performed to investigate the impact of different underfill, on the inelastic strain of the outermost bumps and shear stress in the Cu/low-K layer. JEDEC standard reliability were performed on the test vehicles with different first level interconnects, die thickness, underfill materials and dicing methods.