Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

Copper/Low-k structures are the desired choice for advanced integrated circuits (ICs) as the IC technology trends moving toward finer pitch, higher speed, increased integration and higher performance ICs. Copper interconnects with low-k dielectric material improves the ICs performance by reducing interconnect RC delay, cross talk between adjacent metal lines and power loss. However, low-k materials have intrinsically lower modulus, lower fracture toughness and poorer adhesion compared to the traditional silicon dioxide (SiO2) and silicon nitride (SiN) dielectric material. Thus, The packaging of Cu/low-k IC device is a challenge for packaging industry to integrate these device with out failure during assembly and reliability. More over these advanced high performance ICs requires high density fine pitch off-chip interconnects. Wafer level packaging is one of the promising candidates for the future fine pitch and high performance Cu/Low-K ICs packaging as it can accommodate the high density fine pitch off-chip interconnects at low cost. This work presents, the detailed parametric study to optimize the chip level and package level reliability and wafer level packaging (WLP) process, assembly and package reliability assessment of the Cu/Low-K devices using finite element model (FEM) analysis. To evaluate the Cu/Low-K WLP reliability, 7 mm x 7 mm size die is designed with 128 Input/output off-chips interconnects at 300 mum pitch in two depopulated rows. Test vehicles are fabricated on 200 mm diameter wafer with 15 layers blanket black diamond Low-K stack with one final Cu metal and Al bond pad. Two different Pb free solder interconnects, thick copper column of 100 mum height with SnAg solder cap and SnAg solder bump of 150 mum height with 5 micron thick copper UBM, are fabricated. The Cu/low- K test dies are assembled onto a 2 layer high Tg FR-4 substrate using 2 different types of no-flow underfill to assess the reliability of this Cu/Low-K WLP, various JEDEC standard r- - eliability tests are carried out and failure analysis also performed.