Thermal-Electrical Co-simulation for Wafer-level Chip Scale Package Maximum Bearing Current

As the trend of smaller and higher density packaging technology developing, the wafer-level chip scale package (WLCSP) is becoming the popular choice for device assembly. While many high performance chip often with high power, the power dissipation through the chip also leads to higher die temperatures. With the redistribution layer of the WLCSP getting more narrow and thinner, in order for the devices to perform reliably throughout their lifetime, heat overload has to be taken care. However, through the evaluation of the redistribution layer maximum bearing power/current can avoid this. So the redistribution layer maximum bearing power/current simulation is becoming the major concern for evaluating the performance of WLCSP. In this paper, a thermo-electrical coupling simulation method is firstly proposed to predict the maximum bearing current. To ensure the packages´ thermal reliability, a finite thermal simulation is carried out to predict the maximum power/Current dissipation the package can endure. The simulation process is performed based on JEDEC standard. Three-dimensional finite volume methods are utilized through the commercial code Flotherm. Still air condition is supposed in the simulation. The redistribution layer electrical parasitic parameter-resistance is also extracted by the commercial code Ansoft Q3D. Thus, the maximum and Minimum resistance of the nets which can bear the Maximum Power/Current can be selected.