A novel self-calibration scheme for 12-bit 50MS/s SAR ADC

This paper presents a low-power 12-bit 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using single input condition for Built-In Self Test (BIST) that uses a novel self-calibration scheme to reduce both offset voltage of a comparator and capacitor mismatch of the DAC. The proposed self-calibration scheme changes the offset voltage of the comparator continuously for every step to decide onebit code. The changed offset voltage of the comparator is able to cancel not only inherent offset voltage of the comparator but also the mismatch of DAC. Consequently, the total mismatch error of both the comparator and capacitor of DAC can be reduced. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μm×298μm Using 1.2V supply and the sampling rate of 50 MS/s,.