DocumentCode
2519938
Title
Embedded Wafer Level Ball Grid Array (eWLB)
Author
Meyer, T. ; Ofner, G. ; Bradl, S. ; Brunnbauer, M. ; Hagen, R.
Author_Institution
Infineon AG, Regensburg
fYear
2008
fDate
9-12 Dec. 2008
Firstpage
994
Lastpage
998
Abstract
Wafer Level Packaging (fan-in WLB, Wafer Level Ball Grid Array) is the upcoming future packaging technology with many advantages in comparison to standard Ball Grid Array Packages. Advantages are especially the small package dimensions, excellent electrical and thermal performance, highest package interconnect density and integration possibilities at lowest packaging cost. Today, standard (fan-in) WLBs are the technology of choice mainly for small to medium sized chips with a moderate number of interconnects. The reason for the limited number of interconnects is the need to fit all interconnects on the die in a given terminal pitch. Since this is not generally possible, Infineon has developed a fan-out WLB Technology, called embedded Wafer Level Ball Grid Array (eWLB). The technology is based on a reconstituted wafer which is built prior to the thin-film technology, adding space around the dies to increase the possible number of interconnects on the package. This Reconstituted Wafer is afterwards processed by applying dielectric, redistribution, solder stop and balls in a modified thin-film and backend technology. The new wafer level package concept complies with the directives for environmental friendly technologies like WEEE and RoHS. eWLB passed all performed Standard JEDEC reliability tests without optical or electrical fails on a test vehicle basis. We will introduce recent results of the platform development of the eWLB technology and show the capabilities of Infineon´s molded embedded Wafer Level Package for future system integration.
Keywords
ball grid arrays; wafer level packaging; electrical performance; embedded wafer level ball grid array; package interconnect density; reconstituted wafer; thermal performance; wafer level packaging; Assembly; Costs; Dielectric thin films; Electronics packaging; Integrated circuit packaging; Semiconductor device packaging; Semiconductor thin films; Space technology; Testing; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location
Singapore
Print_ISBN
978-1-4244-2117-6
Electronic_ISBN
978-1-4244-2118-3
Type
conf
DOI
10.1109/EPTC.2008.4763559
Filename
4763559
Link To Document