Title :
10 Gb/s adaptive receive-side near-end and far-end crosstalk cancellation circuitry
Author :
Byungho Min ; Yang, Noah Hae-Woong ; Palermo, Samuel
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
As serial I/O data rates scale above 10 Gb/s, crosstalk between neighboring channels degrades system bit-error rate (BER) performance. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign-sign least-mean square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10-9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm2.
Keywords :
CMOS digital integrated circuits; FIR filters; IIR filters; band-pass filters; continuous time filters; crosstalk; least mean squares methods; BER; CTLE; FIR filter taps; NEXT-FEXT cancellation; SS-LMS; UI timing margin; adaptive receive-side near-end crosstalk cancellation circuitry; aggressor signal coupling; bit rate 10 Gbit/s; continuous-time band-pass filter IIR tap; continuous-time linear equalizer; coupled 4-in FR4 transmission line channels; differentiator circuit; far-end crosstalk cancellation circuitry; filter tap coefficients; frequency-dependent channel loss compensation; general purpose CMOS process; high-speed output buffer; neighboring channels; on-die sign-sign least-mean square adaptation engine; power 34.6 mW; power-detection-based adaptation loop; process-voltage and temperature variations; serial I/O data rates; size 65 nm; system bit-error rate performance; Band-pass filters; Bit error rate; CMOS integrated circuits; Crosstalk; Finite impulse response filters; IIR filters; Transmitters;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908356