A 8 Gbps 0.67mW 1 tap current integrating DFE in 40nm CMOS

Author

Ismail, A. ; Ibrahim, Shadi ; Dessouky, Mohamed

Author_Institution

EECE Dept., Ain Shams Univ., Cairo, Egypt

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

81

Lastpage

84

Abstract

This paper describes the implementation issues in designing a 1 tap current integrating half rate decision feedback equalizer. We introduce a new technique for designing an 8Gbps 1 tap half rate current integrating DFE in 40nm CMOS technology that draws 0.67mW from a 1.1V supply. The technique uses a delayed clock rather than speculation. This removes the speculation impact on power consumption and timing constraints especially in multi tap DFE.

Keywords

CMOS integrated circuits; decision feedback equalisers; integrated circuit design; 1 tap current integrating half rate DFE; 1 tap current integrating half rate decision feedback equalizer; CMOS technology; bit rate 8 Gbit/s; clock delay; multitap DFE; power 0.67 mW; power consumption; size 40 nm; timing constraint; voltage 1.1 V; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delays; Latches; Receivers; DFE; Equalization; half-rate clock; high speed serial links; lossy channel; speculation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908357

Filename

6908357