Title :
Design for improved NBTI reliability of CMOS digital IC
Author :
Lining, Liu ; Bin, Li ; Mingjian, Zhao ; Jiang, Xie
Author_Institution :
Inst. of Microelectron., South China Univ. of Technol., Guangzhou, China
Abstract :
A methodology to mitigate the degradation of digital circuits due to negative bias temperature instability (NBTI) at the view of circuit topology has been put forward in this work. With this approach, simple and strengthened inverter, NAND gate and NOR gate are simulated, the results prove that the proposed strengthened topologies are available to improve NBTI reliability of CMOS digital IC, which is valuable for reliable design against NBTI.
Keywords :
CMOS digital integrated circuits; integrated circuit design; integrated circuit reliability; invertors; logic gates; network topology; thermal analysis; CMOS digital IC; NAND gate; NOR gate; circuit topology; digital circuits; improved NBTI reliability; negative bias temperature instability; reliable design; strengthened inverter; Delay; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Random access memory; Reliability engineering; Circuit delay; Design for Reliability; NBTI;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-9997-7
DOI :
10.1109/EDSSC.2010.5713674
