A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs

This paper presents an energy efficient high speed DAC structure that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. To reduce energy consumption and improve ADC linearity, a segmented pre-quantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of pre-quantization. Time required for one bit cycling is also reduced, which increases the overall conversion speed. A prototype 10-bit 150MS/s SAR ADC with the proposed architecture is implemented in a standard 65nm CMOS technology. According to the simulation, the ADC achieves an SFDR of 82.8 dB and 9.77-bit ENOB with only 1.201 mW power consumption at a 1.2-V supply, resulting in a figure of merit (FOM) of 9.33 fJ/conversion-step.