Title :
Framework of a scalable delay-insensitive asynchronous platform enabling heterogeneous concurrency
Author :
Liang Men ; Jia Di
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA
Abstract :
Parallel architecture of asynchronous circuits has great potential in improving throughput while reducing energy consumption. This paper presents a parallel platform designed using delay-insensitive asynchronous logic. Heterogeneous data processing units as well as datapath control logic are integrated in the platform. All these units share the common data I/O and external handshaking control channels. Asynchronous arbiters are incorporated to make the cores´ data requests mutually exclusive. The highly-modular interface and delay-insensitivity allow the platform to be easily cascaded to construct large systems. Simulation results indicate the functional correctness of the heterogeneous platform as well as its cascaded structure.
Keywords :
asynchronous circuits; delay systems; energy consumption; parallel architectures; asynchronous arbiters; asynchronous circuits; cascaded structure; data I/O; datapath control logic; delay-insensitive asynchronous logic; delay-insensitivity; energy consumption reduction; external handshaking control channels; heterogeneous concurrency platform; heterogeneous data processing units; highly-modular interface; parallel architecture; scalable delay-insensitive asynchronous platform; Asynchronous circuits; Delays; Logic gates; Multicore processing; Multiplexing; Throughput; asynchronous arbiter; asynchronous circuit; cascaded structure; heterogeneous platform;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908365
