• DocumentCode
    2520570
  • Title

    Copper-Pillar Bump-Joint Thermo-Mechanical and Thermal Modeling for Flip-Chip Packages

  • Author

    Mandal, Rathin ; Mui, Y.C.

  • Author_Institution
    Adv. Micro Devices Singapore Pte. Ltd., Singapore, Singapore
  • fYear
    2008
  • fDate
    9-12 Dec. 2008
  • Firstpage
    1184
  • Lastpage
    1189
  • Abstract
    Thermo-mechanical modeling has been done in a true-symmetry three-dimensional geometry for copper-pillar flip-chip packages to find out package warpage, stress and bump joint strain energy during temperature cycling. Lead-free solder materials, SnAg and SnAgCu were used in the bump joint at the substrate side. The strain energy due to both time-independent plastic and creep had been considered during temperature cycling. Ansys FEA modeling was done in two steps. First, a true-symmetry global model was generated. Then, cut boundary sub-modeling technique was applied to find out the stress and strain energy in different critical locations. Different underfill materials revealed that lower coefficient of thermal expansion (CTE) and lower modulus material has low stress in the underfill but strain energy accumulation in the bump during temperature cycling was greater. Bump strain energy accumulation due to bump pitch was also studied and revealed that strain energy accumulation was higher for increasing bump pitch from 150 ¿m to 180 ¿m. Simulation has been done to find the effect of copper pillar height with different underfill and revealed that bump strain energy accumulation varies with the underfill properties. A thermal model was also generated in Flotherm to find the effect of copper pillar thermal performance on flip-chip packages. Copper pillar flip chip packages didn´t show any significant thermal benefit, since most of the heat removal was happening from silicon back side.
  • Keywords
    copper; creep; finite element analysis; flip-chip devices; microassembling; solders; thermal expansion; Cu; FEA; copper-pillar bump-joint; creep; cut boundary sub-modeling; flip-chip packages; lead-free solder materials; strain energy; temperature cycling; thermal expansion coefficient; thermal modeling; thermo-mechanical modeling; true-symmetry global model; Capacitive sensors; Copper; Environmentally friendly manufacturing techniques; Geometry; Lead; Packaging; Solid modeling; Temperature; Thermal stresses; Thermomechanical processes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-2117-6
  • Electronic_ISBN
    978-1-4244-2118-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2008.4763590
  • Filename
    4763590