Title :
Memory efficient VLSI architecture for lifting-based DWT
Author :
Darji, A.D. ; Limaye, Ashutosh
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India
Abstract :
In this paper, a new lifting-based DWT architecture for CDF 9/7 filter is proposed which has lowest temporal memory among the existing architectures. This is achieved with a modified overlapped-scanning method and recalculation of one intermediate DWT coefficient. The proposed architecture requires only 2N temporal memory to process N × N sized image. The architecture has a critical path of one multiplier delay and demonstrates 100% hardware utilization efficiency.
Keywords :
VLSI; application specific integrated circuits; digital signal processing chips; discrete wavelet transforms; image coding; CDF 9/7 filter; critical path; cumulative distribution function; hardware utilization efficiency; lifting-based DWT processor; memory efficient VLSI architecture; multiplier delay; overlapped scanning method; Buffer storage; Discrete wavelet transforms; Memory management; Registers; Very large scale integration;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908384
