FPGA-based coprocessor for text string extraction

In document understanding, one of the early stages involves extracting text strings from a scanned image of the document. Often, the text is printed on a repetitive background of design patterns for visual effects. For recognition purposes, the text strings need to be extracted eliminating the background. Image morphology based algorithms have been proposed for this purpose. However, image morphology operations are compute intensive. We describe the design and synthesis of a high-performance coprocessor to meet the compute load. The algorithm has been synthesized for Splash 2, an attached processor on Sun hosts. The Xilinx Field-Programmable Gate Array (FPGA) based PEs are programmed using VHDL behavioral modeling. The design can run at near-ASIC speeds of ≈22 MHz clock rate with effective timing of 3 milliseconds per 128×128 image frame and 3×3 structuring element. Compared with a SPARC station 20 timings of 1.5 sees, the present implementation has a speed advantage of the order of 500 times