How to use high speed reconfigurable FPGA for real time image processing?

Author

Demigny, Didier ; Kessal, Lounis ; Bourguiba, Riad ; Boudouani, Nassima

Author_Institution

Cergy Pontoise Univ., France

fYear

2000

fDate

2000

Firstpage

240

Lastpage

246

Abstract

In France, ten research teams study and build a hardware architecture (ARDOISE) which is dedicated to real time image processing. This architecture uses fast or dynamic reconfiguration allowed by new FPGA circuits. During a video frame duration, several algorithms are computed sequentially on the same hardware. This paper highlights the architectural concepts used to build ARDOISE. Then an analytical model is defined in order to complete the limits and the performances expected in the use of the dynamic reconfiguration scheme. An example in image segmentation is developed to show a possible partitioning methodology

Keywords

field programmable gate arrays; image segmentation; reconfigurable architectures; ARDOISE; architectural concepts; hardware architecture; high speed reconfigurable FPGA; image segmentation; partitioning methodology; real time image processing; video frame duration; Analytical models; Circuits; Computer architecture; Field programmable gate arrays; Hardware; Image coding; Image processing; Image segmentation; Partitioning algorithms; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 2000. Proceedings. Fifth IEEE International Workshop on

Conference_Location

Padova

Print_ISBN

0-7695-0740-9

Type

conf

DOI

10.1109/CAMP.2000.875983

Filename

875983