Yield aware inter-logic-layer communication in 3-D ICs: Early design stage recommendations

3-D ICs provide more logic space by introducing a multiple tier structure. Through silicon vias (TSVs) are utilized for signal propagation between multiple tiers. However, TSVs are vulnerable to fracture, which leads to lower yield. This paper analyzes different yield aware TSV redundancy techniques from a hardware overhead and effective redundancy perspective. A set of mathematical relationships is derived to obtain a first-order approximation of effective redundancy and hardware design overhead. One of the results indicates that for 250 inter-tier TSV signals, the hardware overhead for 3×3 router based redundancy technique is about 3 times more than 1:4 TSV redundancy technique, while providing 5 times more effective redundancy per cell. Such results provide an early design stage estimate for the ASIC designer. We applied our proposed technique to clock domain crossing (CDC) interfaces.