Average placement method with common centroid constraints for analog IC layout design

To improve immunity against process gradients, a common centroid constraint, in which every pair of capacitors should be placed symmetrically with respect to a common center point, is widely used. Several methods to obtain a good placement satisfying the constraints were proposed. However, the distance between cells in a common centroid group may be redundantly big, and it degrades the immunity. In this paper, we propose a novel algorithm to place cells belonging to each common centroid group. The algorithm is simple, but it is proved to be effective.