Sizing analog integrated circuits by combining gm/ID technique and evolutionary algorithms

Automatic sizing of analog integrated circuits (ICs) remains an open challenge. This work shows an hybrid approach for finding optimal sizes of analog IC´s elements, by combining the g_m/I_D technique for determining the parameter ranges for a given biasing levels, and using those to limit the search space through performing multi-objective optimization with evolutionary algorithms. That way, the NSGA-II optimization algorithm is employed to optimize the width (W) and length (L) of MOSFETs of an operational transconductance amplifier, which (W/L) search spaces are found by applying equations and biasing conditions to the g_m/I_D technique. From simulation results, we conclude on the appropriateness of g_m/I_D to accelerate the computational time of evolutionary algorithms for optimizing analog ICs.