Solving the I/O bandwidth problem in system on a chip testing

Author

Maroufi, Walid ; Benabdenbi, Mounir ; Marzouki, Meryem

Author_Institution

LIP6 Lab., Paris, France

fYear

2000

fDate

2000

Firstpage

9

Lastpage

14

Abstract

The first part of this paper describes the control of CAS-BUS, a P1500 compatible Test Access Mechanism (TAM). Boundary scan features are used to allow controlling of the TAM and the P1500 wrappers. The final architecture characteristics are its flexibility, scalability and reconfigurability. It also allows trade-off to optimize test time and area overhead. The second part deals with a test pin expansion method in order to solve the bandwidth problem. The solution we propose is based on a new compression/decompression mechanism which avoid TAM performances degradation

Keywords

VLSI; application specific integrated circuits; automatic testing; boundary scan testing; data compression; integrated circuit testing; logic testing; microprocessor chips; CAS-BUS; I/O bandwidth problem; P1500 compatible test access mechanism; P1500 wrappers; SOC testing; TAM performances degradation avoidance; architecture characteristics; area overhead optimisation; boundary scan features; compression/decompression mechanism; flexibility; reconfigurability; scalability; system on a chip testing; test pin expansion method; test time optimisation; Bandwidth; Content addressable storage; Degradation; Laboratories; Performance evaluation; Pins; Switches; System testing; System-on-a-chip; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on

Conference_Location

Manaus

Print_ISBN

0-7695-0843-X

Type

conf

DOI

10.1109/SBCCI.2000.876001

Filename

876001