ATG-based timing analysis of circuits containing complex gates

Most of the false path-aware timing analysis algorithms were originally developed for circuits made of simple gates, i.e. ANDs/NANDs, ORs/NORs and inverters. However, the availability of efficient CMOS macrocell generators and “library-free” technology mapping tools has made possible the extensive use of complex gates (mainly static CMOS) in the physical design of large combinational blocks. As a consequence, the ability of handling circuits containing complex gates appears as a highly desirable feature for current timing analysis tools. A common solution to this problem relies on using macro-expansion. Macro-expansion results in loss of accuracy and increase in execution time, however. On the other hand, the direct application of the existing false path aware timing analysis algorithms demands that sensitization conditions take complex gates into account. Currently, the state of the art in false-path aware timing analysis (also called functional timing analysis) is represented by the algorithms based on Automatic Test Generation (ATG-based) and those based on satisfiability (SAT-based). This paper presents an extension to an ATG-based algorithm, the timed-test generation procedure, for performing functional timing analysis of circuits containing complex gates without using macro-expansion